EPM5192AGC vs EPM5192GC84-1 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC par Altera et EPM5192GC84-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC | EPM5192GC84-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $56,00 | $14,20 |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | Shared input/clock and shared product terms |
| Process Technology | CMOS | — |
| Boîtier | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | 84-pin PGA (Pin Grid Array), WPGA code |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal and tolerance] | — |
| Type de montage | Through-hole (Pin Grid Array) | Through-hole (PGA socket) |
| Statut RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | Compliant (per third-party distributor listing) |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Product Type | — | UV-Erasable/OTP Complex PLD (CPLD) |
| Technology | — | CMOS (EPROM-cell based) |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Fréquence d'horloge maximale | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Total Inputs / Outputs | — | 72 inputs / 64 outputs |
| Temperature Grade | — | Commercial |
| Programming Method | — | UV erasure (quartz window) + EPROM programmer |
| Logic Element Type | — | Macrocells with AND/OR array |