EPM5192ALC84-15 vs EPM5192AGC84-20 Comparación
Comparación detallada lado a lado de EPM5192ALC84-15 por Altera y EPM5192AGC84-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192ALC84-15 | EPM5192AGC84-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,20 | $41,20 |
| Device Family | MAX 5000 (EPM5192) | — |
| Device Type | CPLD / UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Propagation Delay (tPD) | 15 ns | — |
| Propagation Delay (Industry Variant) | 25 ns (per MicrochipUSA listing) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS (EPROM-based) | CMOS |
| Programmability | UV-erasable window / OTP | — |
| Encapsulado | 84-pin PLCC (QCCJ, J-bend ceramic) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Operating Temperature Grade | Commercial | Commercial |
| Terminal Form | J-BEND | — |
| Package Code | QCCJ | WPGA |
| Package Shape | SQUARE | — |
| Architecture | Programmable Logic Array + Macrocell Registers + PIA interconnect | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Family | — | MAX 5000 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Tensión de alimentación | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Tipo de montaje | — | Through-Hole (Pin Grid Array socket) |