EPM5192ALC84-15 vs EPM5192AGC84-20 Comparaison
Comparaison détaillée côte à côte de EPM5192ALC84-15 par Altera et EPM5192AGC84-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192ALC84-15 | EPM5192AGC84-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $13,20 | $41,20 |
| Device Family | MAX 5000 (EPM5192) | — |
| Device Type | CPLD / UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Propagation Delay (tPD) | 15 ns | — |
| Propagation Delay (Industry Variant) | 25 ns (per MicrochipUSA listing) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS (EPROM-based) | CMOS |
| Programmability | UV-erasable window / OTP | — |
| Boîtier | 84-pin PLCC (QCCJ, J-bend ceramic) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Operating Temperature Grade | Commercial | Commercial |
| Terminal Form | J-BEND | — |
| Package Code | QCCJ | WPGA |
| Package Shape | SQUARE | — |
| Architecture | Programmable Logic Array + Macrocell Registers + PIA interconnect | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Family | — | MAX 5000 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Tension d'alimentation | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |
| Statut RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Type de montage | — | Through-Hole (Pin Grid Array socket) |