EPM5192AQC100-20 vs EPM5192AQI100-20 Comparación
Comparación detallada lado a lado de EPM5192AQC100-20 por Altera y EPM5192AQI100-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteComparación de especificaciones
| Parámetro | EPM5192AQC100-20 | EPM5192AQI100-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,85 | $18,90 |
| Device Family | MAX 5000 | — |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 192 | — |
| Maximum Operating Frequency | 66.7 MHz | — |
| Propagation Delay (tpd) | 33 ns | — |
| Encapsulado | 100-lead PQFP (R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Terminal Pitch | 0.65 mm | — |
| Process Technology | CMOS | — |
| Programming Technology | UV-Erasable / One-Time-Programmable (OTP) | — |
| Tensión de alimentación | 5 V (typical, MAX 5000 family) | [DATA_NEEDED: VCC range] |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| I/O Count | [DATA_NEEDED: usable I/O count] | — |
| Logic Array Blocks | Multiple LABs (per MAX 5000 architecture) | — |
| Tipo de montaje | Surface Mount (PQFP) | Surface Mount (PQFP) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Family | — | MAX 5000 EPLD |
| Device Series | — | EPM5192 |
| Technology | — | CMOS, UV-erasable EPROM |
| Propagation Delay | — | 20 ns (speed grade -20) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Macrocell Count | — | 192 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 64 bidirectional |
| JEDEC Package Outline | — | R-PQFP-G100 |
| Temperatura de funcionamiento | — | Industrial grade ("I" suffix) |
| Architecture | — | Classic EPLD, deterministic timing |
| Design Tool | — | Altera MAX+PLUS II (legacy) |