EPM5192AQC100-20 vs EPM5192AQI100-20 Comparaison
Comparaison détaillée côte à côte de EPM5192AQC100-20 par Altera et EPM5192AQI100-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteComparaison des spécifications
| Paramètre | EPM5192AQC100-20 | EPM5192AQI100-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,85 | $18,90 |
| Device Family | MAX 5000 | — |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 192 | — |
| Maximum Operating Frequency | 66.7 MHz | — |
| Propagation Delay (tpd) | 33 ns | — |
| Boîtier | 100-lead PQFP (R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Terminal Pitch | 0.65 mm | — |
| Process Technology | CMOS | — |
| Programming Technology | UV-Erasable / One-Time-Programmable (OTP) | — |
| Tension d'alimentation | 5 V (typical, MAX 5000 family) | [DATA_NEEDED: VCC range] |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| I/O Count | [DATA_NEEDED: usable I/O count] | — |
| Logic Array Blocks | Multiple LABs (per MAX 5000 architecture) | — |
| Type de montage | Surface Mount (PQFP) | Surface Mount (PQFP) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Family | — | MAX 5000 EPLD |
| Device Series | — | EPM5192 |
| Technology | — | CMOS, UV-erasable EPROM |
| Propagation Delay | — | 20 ns (speed grade -20) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Macrocell Count | — | 192 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 64 bidirectional |
| JEDEC Package Outline | — | R-PQFP-G100 |
| Température de fonctionnement | — | Industrial grade ("I" suffix) |
| Architecture | — | Classic EPLD, deterministic timing |
| Design Tool | — | Altera MAX+PLUS II (legacy) |