EPM5192AQI100-15 vs EPM5192AQM100-20 Comparación
Comparación detallada lado a lado de EPM5192AQI100-15 por Intel y EPM5192AQM100-20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteComparación de especificaciones
| Parámetro | EPM5192AQI100-15 | EPM5192AQM100-20 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,40 | $8,20 |
| Family | MAX 5000 | — |
| Series | MAX® 5000 EPLD | — |
| Device Type | OT PLD (One-Time-Programmable EPLD), CMOS | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Programmable I/O Lines | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Logical Inputs | 72 | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (max datasheet) | 25 ns | — |
| Maximum Internal Frequency | 83.3 MHz | — |
| Encapsulado | PQFP-100 (R-PQFP-G100), 100-pin Plastic Quad Flat Pack | 100-pin PQFP (JESD-30 code R-PQFP-G100) |
| Operating Temperature Grade | Industrial (-40C to +85C) - 'I' suffix | [DATA_NEEDED: explicit temperature grade from datasheet] |
| Programming Method | JTAG via Altera programming hardware (ByteBlasterMV, USB-Blaster) | — |
| Technology | CMOS, EPROM-based (UV-erasable on windowed versions, OTP on this part) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: verified from manufacturer product page] |
| Tensión de alimentación | [DATA_NEEDED: VCC typical value] | [DATA_NEEDED: VCC range from datasheet] |
| Device Family | — | MAX 5000 (EPLD / classic CPLD) |
| Logic Elements | — | 192 macrocells across 12 Logic Array Blocks (LABs) |
| Number of LABs | — | 12 |
| User I/O Lines | — | 64 |
| Pin-to-Pin Propagation Delay (tPD) | — | 33 ns |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Tipo de montaje | — | Surface Mount |
| Process Technology | — | CMOS EPROM-based |
| Configuration Memory | — | On-chip EPROM (non-volatile, one-time programmable in this package) |
| Boundary-Scan Test | — | JTAG / IEEE 1149.1 compatible |
| External Clock Input | — | Yes (global clock pin) |