EPM5192AQI100-15 vs EPM5192AQM100-20 Comparaison
Comparaison détaillée côte à côte de EPM5192AQI100-15 par Intel et EPM5192AQM100-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteComparaison des spécifications
| Paramètre | EPM5192AQI100-15 | EPM5192AQM100-20 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $21,40 | $8,20 |
| Family | MAX 5000 | — |
| Series | MAX® 5000 EPLD | — |
| Device Type | OT PLD (One-Time-Programmable EPLD), CMOS | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Programmable I/O Lines | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Logical Inputs | 72 | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (max datasheet) | 25 ns | — |
| Maximum Internal Frequency | 83.3 MHz | — |
| Boîtier | PQFP-100 (R-PQFP-G100), 100-pin Plastic Quad Flat Pack | 100-pin PQFP (JESD-30 code R-PQFP-G100) |
| Operating Temperature Grade | Industrial (-40C to +85C) - 'I' suffix | [DATA_NEEDED: explicit temperature grade from datasheet] |
| Programming Method | JTAG via Altera programming hardware (ByteBlasterMV, USB-Blaster) | — |
| Technology | CMOS, EPROM-based (UV-erasable on windowed versions, OTP on this part) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: verified from manufacturer product page] |
| Tension d'alimentation | [DATA_NEEDED: VCC typical value] | [DATA_NEEDED: VCC range from datasheet] |
| Device Family | — | MAX 5000 (EPLD / classic CPLD) |
| Logic Elements | — | 192 macrocells across 12 Logic Array Blocks (LABs) |
| Number of LABs | — | 12 |
| User I/O Lines | — | 64 |
| Pin-to-Pin Propagation Delay (tPD) | — | 33 ns |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Type de montage | — | Surface Mount |
| Process Technology | — | CMOS EPROM-based |
| Configuration Memory | — | On-chip EPROM (non-volatile, one-time programmable in this package) |
| Boundary-Scan Test | — | JTAG / IEEE 1149.1 compatible |
| External Clock Input | — | Yes (global clock pin) |