EPM5192C-2 vs EPM5192JC-1 Comparación
Comparación detallada lado a lado de EPM5192C-2 por Altera y EPM5192JC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192C-2 | EPM5192JC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,20 | $22,40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex Programmable Logic Device (CPLD) | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 84 |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (PIA, typical) | 45 ns | — |
| Maximum Operating Frequency | 50 MHz | — |
| Process Technology | CMOS | — |
| Configuration Memory | EEPROM (non-volatile) | UV-EPROM (erasable under UV lamp) |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -2 | — |
| Programming Interface | JTAG / Altera MAX+ programming | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Estado RoHS | unknown | — |
| Lead-Free | unknown | — |
| Technology | — | CMOS, UV-Erasable / OTP |
| Usable Gates | — | 3750 |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | — | S-CQCC-J84 |
| Temperatura de funcionamiento | — | 0 C to +70 C (commercial) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |