EPM5192GC84-1 vs EPM5192GI84 Comparación
Comparación detallada lado a lado de EPM5192GC84-1 por Altera y EPM5192GI84 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192GC84-1 | EPM5192GI84 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $19,80 |
| Family | MAX 5000 | MAX 5000 |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | — |
| Technology | CMOS (EPROM-cell based) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| Frecuencia de reloj máxima | 50 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Total Inputs / Outputs | 72 inputs / 64 outputs | — |
| Architecture | Shared input/clock and shared product terms | — |
| Encapsulado | 84-pin PGA (Pin Grid Array), WPGA code | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) |
| Temperature Grade | Commercial | Industrial |
| Tipo de montaje | Through-hole (PGA socket) | Through-Hole (PGA socket or PCB pin/peg) |
| Estado RoHS | Compliant (per third-party distributor listing) | [DATA_NEEDED: most legacy PGA parts are non-RoHS] |
| Programming Method | UV erasure (quartz window) + EPROM programmer | — |
| Logic Element Type | Macrocells with AND/OR array | — |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Package Code | — | WPGA |
| Operating Voltage (VCC) | — | 5 V (typical) |
| I/O Logic Compatibility | — | TTL |
| Programmable Flip-Flop Modes | — | D, T, JK, SR |
| Programmability | — | UV-erasable (windowed) / OTP |
| Programming File Format | — | JEDEC map via MAX+PLUS II / A+PLUS |
| Propagation Delay | — | [DATA_NEEDED: tPD in ns] |
| Max User I/O Pins | — | [DATA_NEEDED: usable I/O count for this package] |
| Rango de temperatura de funcionamiento | — | -40 C to +85 C (industrial) |
| Lead-Free | — | [DATA_NEEDED: legacy part, likely contains lead] |
| Number of Terminals | — | 84 |
| Terminal Form | — | PIN/PEG |
| Package Shape | — | SQUARE |