EPM5192GC84-1 vs EPM5192GI84 对比
详细并排对比 EPM5192GC84-1 出自 Altera 和 EPM5192GI84 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192GC84-1 | EPM5192GI84 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $14.20 | $19.80 |
| Family | MAX 5000 | MAX 5000 |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | — |
| Technology | CMOS (EPROM-cell based) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| 最大时钟频率 | 50 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Total Inputs / Outputs | 72 inputs / 64 outputs | — |
| Architecture | Shared input/clock and shared product terms | — |
| 封装 | 84-pin PGA (Pin Grid Array), WPGA code | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) |
| Temperature Grade | Commercial | Industrial |
| 安装类型 | Through-hole (PGA socket) | Through-Hole (PGA socket or PCB pin/peg) |
| RoHS 状态 | Compliant (per third-party distributor listing) | [DATA_NEEDED: most legacy PGA parts are non-RoHS] |
| Programming Method | UV erasure (quartz window) + EPROM programmer | — |
| Logic Element Type | Macrocells with AND/OR array | — |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Package Code | — | WPGA |
| Operating Voltage (VCC) | — | 5 V (typical) |
| I/O Logic Compatibility | — | TTL |
| Programmable Flip-Flop Modes | — | D, T, JK, SR |
| Programmability | — | UV-erasable (windowed) / OTP |
| Programming File Format | — | JEDEC map via MAX+PLUS II / A+PLUS |
| Propagation Delay | — | [DATA_NEEDED: tPD in ns] |
| Max User I/O Pins | — | [DATA_NEEDED: usable I/O count for this package] |
| 工作温度范围 | — | -40 C to +85 C (industrial) |
| Lead-Free | — | [DATA_NEEDED: legacy part, likely contains lead] |
| Number of Terminals | — | 84 |
| Terminal Form | — | PIN/PEG |
| Package Shape | — | SQUARE |