EPM5192GM vs EPM5192GM-2 Comparación
Comparación detallada lado a lado de EPM5192GM por Altera y EPM5192GM-2 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192GM | EPM5192GM-2 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $58,00 | $92,00 |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (PLD) | EPLD (Erasable Programmable Logic Device) |
| Technology | CMOS | — |
| Number of Macrocells | 192 | — |
| Usable Gates | 3,750 | — |
| Pin-to-Pin Delay (tPD) | 15 ns (fastest speed grade); 55 ns (this part) | — |
| Counter Frequency (fCNT) | up to 76.9 MHz | — |
| Propagation Delay (tPD, this part) | 55 ns | — |
| Encapsulado | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) | PGA-84 (Ceramic Pin Grid Array, windowed) |
| Tipo de montaje | Through-Hole (PGA) | Through-hole (PGA socket) |
| Erasure Method | UV (windowed ceramic package) | — |
| Tensión de alimentación | [DATA_NEEDED: typical VCC range] | [DATA_NEEDED: VCC nominal, typically 5 V for MAX 5000] |
| Maximum User I/O | [DATA_NEEDED: exact I/O count for CPGA-84] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: military/industrial grade temperature range] |
| Estado RoHS | Non-compliant (contains lead in ceramic PGA) | [DATA_NEEDED: ceramic PGA with UV window is typically non-RoHS - verify with manufacturer] |
| Process Node | [DATA_NEEDED: CMOS process geometry] | — |
| Programming Interface | JTAG-compatible (per MAX 5000 family) | — |
| Family | — | Altera MAX 5000 |
| Macrocell Count | — | 192 |
| Logic Elements | — | [DATA_NEEDED: logic element count for MAX 5000 family] |
| Propagation Delay (tPD) | — | 55 ns |
| Speed Grade | — | -2 |
| Process Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |
| Recuento de pines | — | 84 |
| Datasheet Page Count | — | 52 |