EPM5192GM vs EPM5192GM-2 Comparaison
Comparaison détaillée côte à côte de EPM5192GM par Altera et EPM5192GM-2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192GM | EPM5192GM-2 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $58,00 | $92,00 |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (PLD) | EPLD (Erasable Programmable Logic Device) |
| Technology | CMOS | — |
| Number of Macrocells | 192 | — |
| Usable Gates | 3,750 | — |
| Pin-to-Pin Delay (tPD) | 15 ns (fastest speed grade); 55 ns (this part) | — |
| Counter Frequency (fCNT) | up to 76.9 MHz | — |
| Propagation Delay (tPD, this part) | 55 ns | — |
| Boîtier | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) | PGA-84 (Ceramic Pin Grid Array, windowed) |
| Type de montage | Through-Hole (PGA) | Through-hole (PGA socket) |
| Erasure Method | UV (windowed ceramic package) | — |
| Tension d'alimentation | [DATA_NEEDED: typical VCC range] | [DATA_NEEDED: VCC nominal, typically 5 V for MAX 5000] |
| Maximum User I/O | [DATA_NEEDED: exact I/O count for CPGA-84] | — |
| Température de fonctionnement | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: military/industrial grade temperature range] |
| Statut RoHS | Non-compliant (contains lead in ceramic PGA) | [DATA_NEEDED: ceramic PGA with UV window is typically non-RoHS - verify with manufacturer] |
| Process Node | [DATA_NEEDED: CMOS process geometry] | — |
| Programming Interface | JTAG-compatible (per MAX 5000 family) | — |
| Family | — | Altera MAX 5000 |
| Macrocell Count | — | 192 |
| Logic Elements | — | [DATA_NEEDED: logic element count for MAX 5000 family] |
| Propagation Delay (tPD) | — | 55 ns |
| Speed Grade | — | -2 |
| Process Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |
| Nombre de broches | — | 84 |
| Datasheet Page Count | — | 52 |