EPM5192GM883B-2 vs EPM5192JC-2 Comparación
Comparación detallada lado a lado de EPM5192GM883B-2 por Altera y EPM5192JC-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192GM883B-2 | EPM5192JC-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $142,00 | $22,50 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device), UV-erasable | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 45 ns |
| Maximum Internal Clock Frequency | 33.3 MHz | — |
| Supply Voltage (VCC, nominal) | 5 V | — |
| Technology | 5 V CMOS | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Encapsulado | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Package Outline | 28.45 mm square (approx.) | — |
| Military Screening | MIL-STD-883 (per '883' suffix) | — |
| Tipo de montaje | Through-hole PGA socket | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Estado RoHS | non_compliant (ceramic CPGA with MIL-STD-883 screening) | [DATA_NEEDED: RoHS compliance] |
| JEDEC Package Code | S-CPGA-P84 | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| External Clock Inputs | — | 1 |
| Frecuencia de reloj máxima | — | 40 MHz |
| Process Technology | — | CMOS |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |