EPM5192GM883B-2 vs EPM5192JC-2 比較
詳細な並列比較: EPM5192GM883B-2 メーカー: Altera および EPM5192JC-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192GM883B-2 | EPM5192JC-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $142.00 | $22.50 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device), UV-erasable | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 45 ns |
| Maximum Internal Clock Frequency | 33.3 MHz | — |
| Supply Voltage (VCC, nominal) | 5 V | — |
| Technology | 5 V CMOS | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| パッケージ | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Package Outline | 28.45 mm square (approx.) | — |
| Military Screening | MIL-STD-883 (per '883' suffix) | — |
| 実装タイプ | Through-hole PGA socket | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | — |
| RoHS ステータス | non_compliant (ceramic CPGA with MIL-STD-883 screening) | [DATA_NEEDED: RoHS compliance] |
| JEDEC Package Code | S-CPGA-P84 | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| External Clock Inputs | — | 1 |
| 最大クロック周波数 | — | 40 MHz |
| Process Technology | — | CMOS |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| 動作温度範囲 | — | [DATA_NEEDED: operating temperature range] |