EPM5192LC-45 vs EPM5192LC-2N Comparación
Comparación detallada lado a lado de EPM5192LC-45 por Altera y EPM5192LC-2N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC-45 | EPM5192LC-2N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $24,00 | $11,85 |
| Family | MAX 5000 | MAX 5000 |
| Series | EPM5192 | — |
| Macrocells | 192 | 192 |
| Logic Elements | 192 macrocells | 192 macrocells (PAL/GAL-style AND-OR array) |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Delay (tPD) | 45 ns | — |
| Dedicated Inputs | [DATA_NEEDED: dedicated input count] | — |
| Programmable I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM / OTP | — |
| Technology | EPROM-based CMOS | — |
| Package Type | LCC (Leaded Ceramic Chip Carrier) with UV window | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Package Code | LC | — |
| Speed Grade | -45 (45 ns tPD) | -2 (tPD approximately 25 ns) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Tensión de alimentación | 5 V | 5 V (typical) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant (per -N lead-free suffix) |
| Tipo de montaje | Surface Mount (LCC) | Surface Mount (LC package) |
| Datasheet Page Count | 52 pages | — |
| Flip-Flops | — | 192 |
| Propagation Delay (typical) | — | 25 ns |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |
| Programming Interface | — | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |