EPM5192LC-45 vs EPM5192LC-2N Comparaison
Comparaison détaillée côte à côte de EPM5192LC-45 par Altera et EPM5192LC-2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192LC-45 | EPM5192LC-2N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $24,00 | $11,85 |
| Family | MAX 5000 | MAX 5000 |
| Series | EPM5192 | — |
| Macrocells | 192 | 192 |
| Logic Elements | 192 macrocells | 192 macrocells (PAL/GAL-style AND-OR array) |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Delay (tPD) | 45 ns | — |
| Dedicated Inputs | [DATA_NEEDED: dedicated input count] | — |
| Programmable I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM / OTP | — |
| Technology | EPROM-based CMOS | — |
| Package Type | LCC (Leaded Ceramic Chip Carrier) with UV window | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Package Code | LC | — |
| Speed Grade | -45 (45 ns tPD) | -2 (tPD approximately 25 ns) |
| Température de fonctionnement | 0C to +70C (commercial) | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Tension d'alimentation | 5 V | 5 V (typical) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant (per -N lead-free suffix) |
| Type de montage | Surface Mount (LCC) | Surface Mount (LC package) |
| Datasheet Page Count | 52 pages | — |
| Flip-Flops | — | 192 |
| Propagation Delay (typical) | — | 25 ns |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |
| Programming Interface | — | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |