EPM570T100C4 vs EPM570T100C3N Comparación
Comparación detallada lado a lado de EPM570T100C4 por Intel y EPM570T100C3N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM570T100C4 | EPM570T100C3N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,40 | $8,10 |
| Family | MAX II | MAX II |
| Logic Elements (LEs) | 570 | 570 |
| Macrocells | 440 | — |
| Maximum User I/O Pins (this package) | 80 | — |
| Pin-to-Pin Propagation Delay (tPD) | 5.4 ns | — |
| User Flash Memory | 8 Kbits | — |
| General-Purpose SRAM | 4.4 Mbits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Encapsulado | TQFP-100 (T100), 14 x 14 mm | 100-TQFP (T100) |
| Temperatura de funcionamiento | 0C to +85C (commercial) | 0 °C to +85 °C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | JTAG / IEEE 1149.1 boundary-scan |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL Level] | — |
| Estado RoHS | Compliant | Compliant |
| On-chip Oscillator | Yes (3.3 MHz / 5.5 MHz selectable) | — |
| Internal Logic Analyzers / ISP | JTAG-based in-system programmable, no external boot PROM required | — |
| Macro Cells | — | 440 |
| Maximum User I/Os | — | 76 |
| Pin-to-Pin Delay (tPD1) | — | 5.4 ns |
| Maximum Internal Frequency | — | 304 MHz |
| User Flash Memory (UFM) | — | 8 Kbits |
| Number of LABs | — | 57 |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) |
| Process Technology | — | 0.18 µm Flash |
| In-System Programmable | — | Yes |
| Speed Grade | — | C3 |