EPM570T100C5 vs EPM570T100A5N Comparación
Comparación detallada lado a lado de EPM570T100C5 por Intel y EPM570T100A5N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM570T100C5 | EPM570T100A5N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,10 | $6,72 |
| Series | MAX II | — |
| Family | MAX II CPLD | — |
| Logic Elements | 570 | 570 |
| Macrocells | 440 | 440 |
| Maximum User I/O Pins | 76 | — |
| Propagation Delay (tpd) | 5.4 ns (max) | — |
| Maximum Frequency | 201.1 MHz | — |
| Process Technology | 0.18 µm | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | — |
| Encapsulado | TQFP-100 (14x14 mm) | 100-pin TQFP |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0°C to 85°C (TJ) | -40 °C to +125 °C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) - ISP |
| Estado RoHS | Compliant | Compliant |
| Device Family | — | MAX II |
| User I/O Pins | — | 76 |
| Number of Logic Array Blocks (LABs) | — | 57 |
| Pin-to-Pin Logic Delay (tPD) | — | 5.4 ns |
| Maximum Internal Frequency | — | 304 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V (typical) |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory (UFM) | — | 8 Kbits |
| Configuration Memory | — | On-chip non-volatile flash |