EPM7096LC84-15 vs EPM7128SLC84-15 Comparación
Comparación detallada lado a lado de EPM7096LC84-15 por Altera y EPM7128SLC84-15 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7096LC84-15 | EPM7128SLC84-15 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $10,40 |
| Family | MAX 7000 | MAX 7000S |
| Series | MAX 7000 (second-generation MAX architecture) | — |
| Macro Cells | 96 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1,800 | 2,500 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| User I/O Pins | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programmable Type | EE PLD (in-system programmable via JTAG) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | JTAG (IEEE Std. 1149.1), in-system programmable |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Encapsulado / Carcasa | 84-PLCC (J-Lead) | — |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) | — |
| Tipo de montaje | Surface Mount | Surface Mount / Socketed (PLCC-84 socket) |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| Erase/Program Endurance | [DATA_NEEDED: erase/program cycle count] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Non-RoHS (legacy 5V part) |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 128 |
| User I/Os | — | 68 (in 84-PLCC) |
| Encapsulado | — | 84-Pin PLCC (J-Lead, J84) |
| Speed Grade | — | -15 (15 ns pin-to-pin delay) |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Internal Frequency (fMAX) | — | 76.9 MHz |
| Logic Family / Process | — | CMOS, 5V, EEPROM |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Standard Support | — | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) |
| Configuration Memory | — | Non-volatile EEPROM (instant-on, no boot PROM) |