EPM7096LC84-15 vs EPM7128SLC84-15 Comparaison
Comparaison détaillée côte à côte de EPM7096LC84-15 par Altera et EPM7128SLC84-15 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM7096LC84-15 | EPM7128SLC84-15 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,85 | $10,40 |
| Family | MAX 7000 | MAX 7000S |
| Series | MAX 7000 (second-generation MAX architecture) | — |
| Macro Cells | 96 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1,800 | 2,500 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| User I/O Pins | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programmable Type | EE PLD (in-system programmable via JTAG) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | JTAG (IEEE Std. 1149.1), in-system programmable |
| Température de fonctionnement | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Boîtier / Format | 84-PLCC (J-Lead) | — |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) | — |
| Type de montage | Surface Mount | Surface Mount / Socketed (PLCC-84 socket) |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| Erase/Program Endurance | [DATA_NEEDED: erase/program cycle count] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Non-RoHS (legacy 5V part) |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 128 |
| User I/Os | — | 68 (in 84-PLCC) |
| Boîtier | — | 84-Pin PLCC (J-Lead, J84) |
| Speed Grade | — | -15 (15 ns pin-to-pin delay) |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Internal Frequency (fMAX) | — | 76.9 MHz |
| Logic Family / Process | — | CMOS, 5V, EEPROM |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Standard Support | — | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) |
| Configuration Memory | — | Non-volatile EEPROM (instant-on, no boot PROM) |