EPM7128AETC144-7 vs EPM7128ATC144-10 Comparación
Comparación detallada lado a lado de EPM7128AETC144-7 por Intel y EPM7128ATC144-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7128AETC144-7 | EPM7128ATC144-10 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,40 | $9,10 |
| Series | MAX 7000A | MAX 7000A |
| Programmable Type | In-System Programmable (ISP), EEPROM | EE PLD (EEPROM-based, in-system programmable) |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/Os | 100 | — |
| Propagation Delay (tPD) Max | 7.5 ns | — |
| Maximum Operating Frequency | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Encapsulado | 144-pin TQFP (20x20 mm) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG (ByteBlaster / USB-Blaster) | — |
| Configuration Memory | EEPROM, non-volatile | — |
| ISP Endurance | 100 cycles typical per macrocell | — |
| Process Technology | CMOS | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | unknown (legacy Altera device) |
| Manufacturer | — | Altera (now Intel) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Array Blocks | — | 4 |
| User I/O Pins | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 98 MHz |
| Supply Voltage - Internal (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage Levels | — | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) |
| In-System Programmability | — | Yes (IEEE Std 1149.1 JTAG) |
| Encapsulado / Carcasa | — | 144-TQFP (20 x 20 mm) |
| Architecture | — | Multiple Array Matrix (MAX), 2nd generation |