EPM7128AETI144-10N vs EPM7128AETC144-7 Comparación
Comparación detallada lado a lado de EPM7128AETI144-10N por Altera y EPM7128AETC144-7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
EPM7128AETI144-10N ObsoleteComparación de especificaciones
| Parámetro | EPM7128AETI144-10N | EPM7128AETC144-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $23,10 | $16,40 |
| Family | MAX 7000A | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum User I/O Pins | 100 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | 3.0 V to 3.6 V |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG Interface | IEEE Std 1149.1 BST compliant | — |
| Encapsulado | TQFP-144 (144-pin) | 144-pin TQFP (20x20 mm) |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0C to +70C (Commercial) |
| Process Technology | 0.35 µm CMOS EEPROM | CMOS |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 3 | — |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Speed Grade | -10 (10 ns tPD) | — |
| Operating Frequency (fCNT) | [DATA_NEEDED: fCNT counter frequency] | — |
| Series | — | MAX 7000A |
| Programmable Type | — | In-System Programmable (ISP), EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Number of Usable Gates | — | 2,500 |
| Number of I/Os | — | 100 |
| Propagation Delay (tPD) Max | — | 7.5 ns |
| Maximum Operating Frequency | — | 129.9 MHz |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V tolerant |
| Programming Interface | — | IEEE 1149.1 JTAG (ByteBlaster / USB-Blaster) |
| Configuration Memory | — | EEPROM, non-volatile |
| ISP Endurance | — | 100 cycles typical per macrocell |