EPM7128ATI100-10 vs EPM7128AETC100-10N Comparación
Comparación detallada lado a lado de EPM7128ATI100-10 por Altera y EPM7128AETC100-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
EPM7128ATI100-10 ⚠ Última compraIntel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteComparación de especificaciones
| Parámetro | EPM7128ATI100-10 | EPM7128AETC100-10N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,85 | $9,95 |
| Series | MAX 7000A | EPM7128AE |
| Family | MAX 7000A (MAX II of MAX 7000 series) | MAX 7000AE |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) | — |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 2,500 | 2500 |
| Number of I/O Pins | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Standard | MultiVolt (2.5V / 3.3V / 5.0V tolerant) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Temperatura de funcionamiento | -40C to +85C (Industrial, 'I' suffix) | 0C to +70C (commercial) |
| Encapsulado | 100-pin TQFP (14x14 mm) | TQFP-100 |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Estado RoHS | Non-compliant (legacy part) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Macrocells | — | 128 |
| Logic Array Blocks | — | 16 |
| User I/Os | — | 84 |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Tolerance | — | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Speed Grade | — | -10 |
| Maximum Frequency | — | [DATA_NEEDED: maximum toggle frequency] |
| Programming | — | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Architecture | — | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | — | Yes (33 MHz, -10 grade per PCI SIG 2.2) |