EPM7128SQC100-10N vs EPM7128AETC100-10N Comparación
Comparación detallada lado a lado de EPM7128SQC100-10N por Altera y EPM7128AETC100-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteComparación de especificaciones
| Parámetro | EPM7128SQC100-10N | EPM7128AETC100-10N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,95 | $9,95 |
| Family | MAX 7000 | MAX 7000AE |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 100 MHz | [DATA_NEEDED: maximum toggle frequency] |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | — |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| Encapsulado | 100-pin PQFP (BQFP) | TQFP-100 |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| Series | — | EPM7128AE |
| Macrocells | — | 128 |
| Logic Array Blocks | — | 16 |
| User I/Os | — | 84 |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Tolerance | — | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Speed Grade | — | -10 |
| Programming | — | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Process Technology | — | CMOS EEPROM |
| Architecture | — | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | — | Yes (33 MHz, -10 grade per PCI SIG 2.2) |