EPM7160SQC160-7 vs EPM7160EQC160-12 Comparación
Comparación detallada lado a lado de EPM7160SQC160-7 por Altera y EPM7160EQC160-12 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7160SQC160-7 | EPM7160EQC160-12 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $9,75 |
| Family | MAX 7000S | MAX 7000E |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 10 | 4 |
| Usable System Gates | 3,200 | — |
| Product Terms per Macrocell | 32 | — |
| Maximum User I/Os | 104 | — |
| Global Clocks | 2 | 4 |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Propagation Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) | — |
| Temperatura de funcionamiento | 0 °C to 70 °C (commercial) | 0 °C to +70 °C (Commercial) |
| Encapsulado | 160-pin PQFP (BQFP, 28x28 mm) | PQFP-160 (EQC), Gull-Wing |
| Tipo de montaje | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| Estado RoHS | Not Compliant (per Arrow listing) | [DATA_NEEDED: RoHS status] |
| Part Status | Obsolete | — |
| Usable Gates | — | 3,200 |
| User I/O Pins | — | 104 |
| Pin-to-Pin Logic Delay (tPD) | — | 12 ns |
| I/O Voltage | — | 5.0 V |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| Non-volatile Configuration | — | EEPROM |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |