EPM7192EGM160-15 vs EPM7192EQC160-20 Comparación
Comparación detallada lado a lado de EPM7192EGM160-15 por Altera y EPM7192EQC160-20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteComparación de especificaciones
| Parámetro | EPM7192EGM160-15 | EPM7192EQC160-20 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $36,80 | $58,26 |
| Family | MAX 7000 | — |
| Sub-family | MAX 7000E | — |
| Device | EPM7192E | — |
| Macrocells | 192 | — |
| Usable Gates | 3750 | — |
| Logic Array Blocks (LABs) | 12 (16 macrocells each) | — |
| User I/O Pins | 124 | — |
| Encapsulado | 160-pin PGA (Pin Grid Array), ceramic | — |
| Pin-to-Pin Logic Delay (tPD) | 15 ns | — |
| Supply Voltage (Core) | 5 V ±5% | — |
| I/O Voltage | 3.3 V or 5 V configurable | — |
| Technology | CMOS EEPROM (0.5 µm) | — |
| Programming Interface | JTAG (ByteBlaster / BitBlaster) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Tipo de montaje | Through-hole (PGA socket) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - non-RoHS era part] |
| Series | — | MAX 7000 |
| Programmable Type | — | EE PLD (EEPROM-based) |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of User I/O Pins | — | 124 (per package), 36 (per data source variant description) |
| Delay Time (tPD) | — | 20 ns |
| Internal Counter Frequency (fCNT) | — | 100 MHz typical |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Encapsulado / Carcasa | — | 160-BQFP / 160-PQFP (28x28 mm) |
| In-System Programmable (ISP) | — | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) |
| Programmable Security Bit | — | Yes |
| Power-Saving Mode | — | Yes, programmable per macrocell |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |