EPM7192EGM160-15 vs EPM7192EQC160-20 对比

详细并排对比 EPM7192EGM160-15 出自 Altera 和 EPM7192EQC160-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7192EGM160-15 EPM7192EQC160-20
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $36.80 $58.26
Family MAX 7000 —
Sub-family MAX 7000E —
Device EPM7192E —
Macrocells 192 —
Usable Gates 3750 —
Logic Array Blocks (LABs) 12 (16 macrocells each) —
User I/O Pins 124 —
封装 160-pin PGA (Pin Grid Array), ceramic —
Pin-to-Pin Logic Delay (tPD) 15 ns —
Supply Voltage (Core) 5 V ±5% —
I/O Voltage 3.3 V or 5 V configurable —
Technology CMOS EEPROM (0.5 µm) —
Programming Interface JTAG (ByteBlaster / BitBlaster) —
工作温度 [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
安装类型 Through-hole (PGA socket) Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - non-RoHS era part]
Series — MAX 7000
Programmable Type — EE PLD (EEPROM-based)
Number of Macrocells — 192
Number of Logic Array Blocks — 4
Number of User I/O Pins — 124 (per package), 36 (per data source variant description)
Delay Time (tPD) — 20 ns
Internal Counter Frequency (fCNT) — 100 MHz typical
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
封装 / 外壳 — 160-BQFP / 160-PQFP (28x28 mm)
In-System Programmable (ISP) — Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1)
Programmable Security Bit — Yes
Power-Saving Mode — Yes, programmable per macrocell
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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