EPM7256AETC100-10N vs EPM7256AETI100-7N Comparación
Comparación detallada lado a lado de EPM7256AETC100-10N por Altera y EPM7256AETI100-7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7256AETC100-10N - 256-Macro MAX 7000A CPLD, 10ns, TQFP-100 | Intel (Altera)
EPM7256AETC100-10N ObsoleteIntel
EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel
EPM7256AETI100-7N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7256AETC100-10N | EPM7256AETI100-7N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,10 | $34,20 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | 5,000 |
| Maximum User I/Os | 84 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | 126.6 MHz |
| Supply Voltage (Core) | 3.3 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | — |
| Programmability | EEPROM, in-system via JTAG (IEEE 1149.1) | In-system programmable via JTAG (IEEE 1149.1) |
| Encapsulado | 100-pin TQFP | 100-pin TQFP (TQ100, 14x14 mm, 0.5 mm pitch) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] | — |
| Process Technology | 0.30 µm EEPROM | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Estado RoHS | [DATA_NEEDED: not confirmed in provided data] | Compliant |
| Lead-Free / Pb-Free | [DATA_NEEDED: not confirmed in provided data] | — |
| Macrocells | — | 256 |
| Maximum User I/O | — | 84 |
| Logic Elements / Blocks | — | 16 Logic Array Blocks |
| Propagation Delay (tPD) | — | 7.5 ns |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| Technology | — | CMOS, EEPROM-based configuration |
| Temperatura de funcionamiento | — | -40C to +85C (Industrial) |
| Nivel MSL | — | 3 (168 hours) |