EPM7256AETC100-10N vs EPM7256AETI100-7N 比較
詳細な並列比較: EPM7256AETC100-10N メーカー: Altera および EPM7256AETI100-7N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7256AETC100-10N - 256-Macro MAX 7000A CPLD, 10ns, TQFP-100 | Intel (Altera)
EPM7256AETC100-10N ObsoleteIntel
EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel
EPM7256AETI100-7N ⚠ ラストタイムバイ仕様比較
| パラメータ | EPM7256AETC100-10N | EPM7256AETI100-7N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $13.10 | $34.20 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | 5,000 |
| Maximum User I/Os | 84 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | 126.6 MHz |
| Supply Voltage (Core) | 3.3 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | — |
| Programmability | EEPROM, in-system via JTAG (IEEE 1149.1) | In-system programmable via JTAG (IEEE 1149.1) |
| パッケージ | 100-pin TQFP | 100-pin TQFP (TQ100, 14x14 mm, 0.5 mm pitch) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] | — |
| Process Technology | 0.30 µm EEPROM | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| RoHS ステータス | [DATA_NEEDED: not confirmed in provided data] | Compliant |
| Lead-Free / Pb-Free | [DATA_NEEDED: not confirmed in provided data] | — |
| Macrocells | — | 256 |
| Maximum User I/O | — | 84 |
| Logic Elements / Blocks | — | 16 Logic Array Blocks |
| Propagation Delay (tPD) | — | 7.5 ns |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| Technology | — | CMOS, EEPROM-based configuration |
| 動作温度 | — | -40C to +85C (Industrial) |
| MSLレベル | — | 3 (168 hours) |