EPM7256AETC100-5N vs EPM7256AEFC100-7 Comparación
Comparación detallada lado a lado de EPM7256AETC100-5N por Altera y EPM7256AEFC100-7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7256AETC100-5N | EPM7256AEFC100-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $15,20 |
| Family | MAX 7000A | MAX 7000A |
| Series | MAX 7000AE | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 256 | 256 |
| Usable Gates | 5000 (range 600 to 10000) | 5,000 |
| User I/Os | 84 | 84 |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 5.0 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | — |
| Encapsulado | TQFP-100 (1.0 mm pitch, 14x14 mm) | 100-pin FBGA (11x11 mm) |
| Tipo de montaje | Surface Mount | Surface Mount (FBGA) |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +90C (commercial) |
| Program Memory | Internal EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Estado RoHS | Compliant (lead-free) | [DATA_NEEDED: rohs status] |
| Nivel MSL | 3 (168 hours) | [DATA_NEEDED: msl level] |
| Process Technology | CMOS, EEPROM-based | — |
| Security Bit | Programmable | — |
| Logic Array Blocks | — | 16 |
| Recuento de pines | — | 100 |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage - VCCIO | — | 2.5 V, 3.3 V, or 5 V (MultiVolt) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal Toggle Rate | — | 250 MHz |
| Maximum Operating Frequency | — | 126.6 MHz |
| Programmable Type | — | In-System Programmable (EEPROM) |
| Programming Interface | — | IEEE 1149.1 JTAG |