EPM7256SQC208-10 vs EPM7256SQC208-7 Comparación
Comparación detallada lado a lado de EPM7256SQC208-10 por Intel y EPM7256SQC208-7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7256SQC208-10 - MAX 7000S CPLD, 256 Macrocells, 10ns, 208-PQFP | Intel
EPM7256SQC208-10 ObsoleteComparación de especificaciones
| Parámetro | EPM7256SQC208-10 | EPM7256SQC208-7 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,20 | $0,00 |
| Series | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5,000 | 5,000 |
| Number of I/O Pins | 164 | — |
| Propagation Delay (tPD) | 10 ns | 7.5 ns |
| Counter Speed (fCNT) | Up to 175.4 MHz | — |
| Encapsulado | 208-pin PQFP (SQC208) | 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programmable Technology | EEPROM (in-system programmable) | — |
| JTAG Support (IEEE 1149.1) | Yes | — |
| PCI Compliance | PCI Local Bus Specification 2.2 compliant | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Nivel MSL | 3 (168 hours) | [DATA_NEEDED: MSL level] |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 7000S (EPM7256S) |
| User I/O Pins | — | 164 |
| Maximum Operating Frequency (fMAX) | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Rango de temperatura de funcionamiento | — | Commercial (0C to +70C) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Speed Grade | — | -7 (7.5 ns) |
| Logic Levels | — | 5.0 V CMOS/TTL compatible |