EPM7256SQC208-15N vs EPM7256SQC208-7N Comparación
Comparación detallada lado a lado de EPM7256SQC208-15N por Altera y EPM7256SQC208-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7256SQC208-15N | EPM7256SQC208-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $27,20 |
| Series | MAX 7000S | — |
| Macrocells | 256 | 256 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay | 15 ns (speed grade -15) | — |
| Tensión de alimentación | 5 V | — |
| Encapsulado | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM (no external config needed) |
| JTAG Interface | IEEE 1149.1 boundary-scan | IEEE 1149.1 boundary-scan (ISP capable) |
| In-System Programmability | Yes (ISP) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| Estado RoHS | Lead free / RoHS Compliant | Compliant (N suffix = lead-free) |
| Logic Array Blocks | 16 macrocells per LAB | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -15 | -7 (7.5 ns pin-to-pin) |
| Product Category | CPLD - Complex Programmable Logic Devices | — |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Family | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 5,000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Open-Drain Output | — | Optional per I/O pin |