EPM7256SQC208-15N vs EPM7256SQC208-7N 비교
다음의 상세 나란히 비교: EPM7256SQC208-15N 제조: Altera 및 EPM7256SQC208-7N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM7256SQC208-15N | EPM7256SQC208-7N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $0.00 | $27.20 |
| Series | MAX 7000S | — |
| Macrocells | 256 | 256 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay | 15 ns (speed grade -15) | — |
| 공급 전압 | 5 V | — |
| 패키지 | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| 실장 유형 | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM (no external config needed) |
| JTAG Interface | IEEE 1149.1 boundary-scan | IEEE 1149.1 boundary-scan (ISP capable) |
| In-System Programmability | Yes (ISP) | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| RoHS 상태 | Lead free / RoHS Compliant | Compliant (N suffix = lead-free) |
| Logic Array Blocks | 16 macrocells per LAB | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -15 | -7 (7.5 ns pin-to-pin) |
| Product Category | CPLD - Complex Programmable Logic Devices | — |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Family | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 5,000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Open-Drain Output | — | Optional per I/O pin |