EPM9320LC84-15 vs EPM9320LC84-10 Comparación
Comparación detallada lado a lado de EPM9320LC84-15 por Intel y EPM9320LC84-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320LC84-15 | EPM9320LC84-10 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,95 | $84,96 |
| Family | MAX 9000 | MAX 9000 EPLD |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6000 (typical) |
| Logic Array Blocks (LABs) | 20 | 16 |
| Propagation Delay (tPD) | 15 ns (max) | — |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V (typical, see datasheet) |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Encapsulado | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (JEDEC MO-047) |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket also common) |
| Temperatura de funcionamiento | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| Estado RoHS | [DATA_NEEDED: confirm from manufacturer] | ROHS3 Compliant (per fpgalink listing) |
| Device | — | EPM9320 |
| Maximum User I/O Pins | — | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Process Technology | — | 0.7 µm CMOS EEPROM/UV-EPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Configuration | — | Non-volatile EEPROM (instant-on, no boot PROM) |
| Nivel de sensibilidad a la humedad (MSL) | — | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | — | 1-7 days (per fpgalink listing) |