EPM9320LC84-20 vs EPM9320ALC84-20 Comparación
Comparación detallada lado a lado de EPM9320LC84-20 por Altera y EPM9320ALC84-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320LC84-20 | EPM9320ALC84-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $10,50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Encapsulado | PLCC-84 (Plastic Leaded Chip Carrier) | PLCC-84 |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Counter Frequency | 118 MHz | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Temperatura de funcionamiento | 0 C to 70 C | [DATA_NEEDED: commercial or industrial grade] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: per Altera datasheet] |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Process Technology | — | 0.5 µm CMOS EEPROM |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Tipo de montaje | — | Surface Mount (PLCC socket compatible) |
| Configuration Memory | — | Non-volatile EEPROM |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |