EPM9320LI84-20 vs EPM9560ELI84-20 Comparación
Comparación detallada lado a lado de EPM9320LI84-20 por Altera y EPM9560ELI84-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560ELI84-20 - MAX 9000 6k-Gate EPLD, 84-Pin PLCC | Intel / Altera
EPM9560ELI84-20 ObsoleteComparación de especificaciones
| Parámetro | EPM9320LI84-20 | EPM9560ELI84-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $12,80 | $19,50 |
| Manufacturer | Altera (acquired by Intel) | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 560 |
| User I/Os | 60 | — |
| Encapsulado | 84-PLCC (J-Lead, plastic LCC) | 84-pin PLCC |
| Propagation Delay (tPD) | 20 ns | — |
| Internal Frequency | 118 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Logic Family | CMOS, EEPROM-based | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) - EEPROM-based |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | 5.0 V ISP via IEEE 1149.1 JTAG |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount (PLCC socket-compatible) | Through-Hole / Socket |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Process Technology | High-performance CMOS EEPROM | CMOS EEPROM |
| Usable Gates | — | 6,000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 212 (package-dependent) |
| Flip-Flops | — | 212 |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Speed Grade | — | -20 |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Standards | — | 5.0 V, 3.3 V, 2.5 V (multiVolt I/O) |