EPM9320RC208-20 vs EPM9320ARC208-10 Comparación
Comparación detallada lado a lado de EPM9320RC208-20 por Altera y EPM9320ARC208-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320RC208-20 | EPM9320ARC208-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,90 | $21,40 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| Usable Gates | 6,000 | 6,000 |
| Maximum I/O Pins | 132 | — |
| Propagation Delay (tPD max) | 20 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Programming Technology | EEPROM, in-system programmable (ISP) | — |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | — |
| Temperatura de funcionamiento | 0 °C to 70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| Encapsulado | 208-RQFP, exposed pad (208-BFQFP) | RQFP-208 (Power Quad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | — |
| Process Technology | CMOS, 5.0 V EEPROM | — |
| Reprogrammability | Yes, unlimited ISP cycles | — |
| Device Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 144.9 MHz |
| Tensión de alimentación | — | 5.0 V |
| Logic Blocks (LABs) | — | 16 |
| Programmability | — | EEPROM, in-system programmable via JTAG |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | — | Per-macrocell programmable, 50% power mode available |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance status] |