EPM9480RC240-20 vs EPM9480RC240-15 Comparación
Comparación detallada lado a lado de EPM9480RC240-20 por Altera y EPM9480RC240-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9480RC240-20 | EPM9480RC240-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,40 | $91,68 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 480 | — |
| Usable Gates | 10,000 | 12,000 |
| Logic Elements | 30 | — |
| User I/O Pins | 175 | — |
| Number of Terminals | 240 | — |
| Encapsulado | 240-RQFP (32x32 mm, FQFP, Gull Wing) | 240-pin RQFP (32x32 mm) |
| Maximum Propagation Delay (tpd) | 20 ns | — |
| Maximum Internal Frequency (fMAX, related -C variant) | 100 MHz | — |
| Programmable Flip-Flops (family) | 676 | — |
| Internal Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| I/O Signaling Levels | 3.3 V or 5 V (configurable) | — |
| Process Technology | CMOS EEPROM | — |
| Programming Interface | In-System Programmable (ISP) via IEEE 1149.1 JTAG | — |
| Operating Temperature Grade | Commercial | — |
| Terminal Form | Gull Wing | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | RoHS non-compliant |
| Programmable Type | — | In System Programmable (ISP) |
| Device Family | — | MAX 9000 |
| Macro Cells | — | 480 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Supplier Device Package | — | 240-RQFP (32x32) |
| Tipo de montaje | — | Surface Mount |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Lead Free Status | — | [DATA_NEEDED: lead free status] |
| Logic Architecture | — | Multiple Array MatriX (MAX) third-generation |
| Supply Voltage (5.0 V nominal) | — | 5.0 V |