EPM9480RC240-20 vs EPM9480RC240-15 Comparaison
Comparaison détaillée côte à côte de EPM9480RC240-20 par Altera et EPM9480RC240-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9480RC240-20 | EPM9480RC240-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,40 | $91,68 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 480 | — |
| Usable Gates | 10,000 | 12,000 |
| Logic Elements | 30 | — |
| User I/O Pins | 175 | — |
| Number of Terminals | 240 | — |
| Boîtier | 240-RQFP (32x32 mm, FQFP, Gull Wing) | 240-pin RQFP (32x32 mm) |
| Maximum Propagation Delay (tpd) | 20 ns | — |
| Maximum Internal Frequency (fMAX, related -C variant) | 100 MHz | — |
| Programmable Flip-Flops (family) | 676 | — |
| Internal Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| I/O Signaling Levels | 3.3 V or 5 V (configurable) | — |
| Process Technology | CMOS EEPROM | — |
| Programming Interface | In-System Programmable (ISP) via IEEE 1149.1 JTAG | — |
| Operating Temperature Grade | Commercial | — |
| Terminal Form | Gull Wing | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | RoHS non-compliant |
| Programmable Type | — | In System Programmable (ISP) |
| Device Family | — | MAX 9000 |
| Macro Cells | — | 480 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Supplier Device Package | — | 240-RQFP (32x32) |
| Type de montage | — | Surface Mount |
| Température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Lead Free Status | — | [DATA_NEEDED: lead free status] |
| Logic Architecture | — | Multiple Array MatriX (MAX) third-generation |
| Supply Voltage (5.0 V nominal) | — | 5.0 V |