EPM9560ARC208-10N vs EPM9560ARC208-10 Comparación
Comparación detallada lado a lado de EPM9560ARC208-10N por Altera y EPM9560ARC208-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560ARC208-10N | EPM9560ARC208-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,20 | $0,00 |
| Family | MAX 9000 | — |
| Macrocells | 560 | 560 macrocells |
| Usable Gates | 12,000 | 12,000 gates |
| User I/O Pins | 153 | 153 I/O |
| Pin-to-Pin Delay | 10 ns | — |
| Internal Counter Frequency | 144.9 MHz | — |
| Tensión de alimentación | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Encapsulado | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | — |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | — |
| Estado RoHS | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Device Family | — | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks | — | 35 LABs |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Frequency | — | 144.9 MHz |
| Logic Family | — | CMOS |
| Configuration Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP) |
| Recuento de pines | — | 208 pins |