EPM9560ARC208-10N vs EPM9560ARC208-10 Comparison
Detailed side-by-side comparison of EPM9560ARC208-10N by Altera and EPM9560ARC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560ARC208-10N | EPM9560ARC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Macrocells | 560 | 560 macrocells |
| Usable Gates | 12,000 | 12,000 gates |
| User I/O Pins | 153 | 153 I/O |
| Pin-to-Pin Delay | 10 ns | — |
| Internal Counter Frequency | 144.9 MHz | — |
| Supply Voltage | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Package | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | — |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | — |
| RoHS Status | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Device Family | — | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks | — | 35 LABs |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Frequency | — | 144.9 MHz |
| Logic Family | — | CMOS |
| Configuration Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP) |
| Pin Count | — | 208 pins |