EPM9560GI280-15 vs EPM9560GI280-20 Comparación
Comparación detallada lado a lado de EPM9560GI280-15 por Intel y EPM9560GI280-20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560GI280-15 | EPM9560GI280-20 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $110,00 | $162,50 |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM, third-generation Multiple Array MatriX (MAX) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | 772 |
| User I/Os | 216 | — |
| Dedicated Inputs | 12 | — |
| Logic Elements / Gates | 12,000 usable gates | — |
| Internal Frequency (fMAX) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns | — |
| Clock-to-Output (tCO) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (3.3 V or 5 V I/O) | — |
| In-System Programmability | 5.0-V ISP via JTAG | Yes (IEEE Std. 1149.1 JTAG) |
| Encapsulado | 280-pin PGA (ceramic, metal-sealed cofired) | 280-pin PGA (PIN/PEG, square) |
| Temperatura de funcionamiento | -40 °C to 85 °C (industrial) | — |
| Process Technology | CMOS EEPROM | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status for GI PGA package] |
| Nivel de sensibilidad a la humedad (MSL) | MSL-3 (168 hours) | — |
| Technology Node | — | 5.0 V CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 28 (16 macrocells each) |
| Usable Gates | — | 12,000 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Delay (Speed Grade) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programming Technology | — | EEPROM (non-volatile) |
| Terminal Form | — | PIN/PEG (through-hole PGA) |
| Package Code | — | PGA |
| Temperature Grade | — | Industrial |
| I/O Pin DC Input Range | — | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | — | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | — | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | — | Monotonic rise |
| Development Tool | — | Altera MAX+PLUS II |
| Supported HDLs | — | VHDL, Verilog HDL, AHDL |