EPM9560R1208-20 vs EPM9560ARC208-10 Comparación
Comparación detallada lado a lado de EPM9560R1208-20 por Altera y EPM9560ARC208-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560R1208-20 | EPM9560ARC208-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,40 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 12,000 gates |
| Macrocells | 560 | 560 macrocells |
| Logic Array Blocks | 52 (typical for 560 macrocells) | 35 LABs |
| Maximum User I/O | 212 | — |
| Propagation Delay (tPD) | 20 ns | 10 ns (speed grade -10) |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Encapsulado | R-1208 (BGA-style fine-pitch) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Tipo de montaje | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | — |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | — |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Estado RoHS | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | — | 153 I/O |
| Internal Frequency | — | 144.9 MHz |
| Tensión de alimentación | — | 5.0 V |
| Logic Family | — | CMOS |
| Configuration Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP) |
| Recuento de pines | — | 208 pins |