EPM9560R1208-20 vs EPM9560ARC208-10 Comparaison
Comparaison détaillée côte à côte de EPM9560R1208-20 par Altera et EPM9560ARC208-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560R1208-20 | EPM9560ARC208-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $22,40 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 12,000 gates |
| Macrocells | 560 | 560 macrocells |
| Logic Array Blocks | 52 (typical for 560 macrocells) | 35 LABs |
| Maximum User I/O | 212 | — |
| Propagation Delay (tPD) | 20 ns | 10 ns (speed grade -10) |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Température de fonctionnement | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Boîtier | R-1208 (BGA-style fine-pitch) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Type de montage | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | — |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | — |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Statut RoHS | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | — | 153 I/O |
| Internal Frequency | — | 144.9 MHz |
| Tension d'alimentation | — | 5.0 V |
| Logic Family | — | CMOS |
| Configuration Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP) |
| Nombre de broches | — | 208 pins |