EPM9560RC208-10 vs EPM9560RC208-21 Comparación
Comparación detallada lado a lado de EPM9560RC208-10 por Intel y EPM9560RC208-21 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM9560RC208-21 - MAX 9000 CPLD, 560 Macrocells, 208-Pin RQFP | Intel (Altera)
EPM9560RC208-21 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM9560RC208-10 | EPM9560RC208-21 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,40 | $22,95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 212 (208-pin package variant) | — |
| Usable Gates | 12,000 | 12,000 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: internal toggle frequency in MHz] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standards Supported | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) | — |
| Configuration Memory | EEPROM (in-system programmable via JTAG) | EEPROM (non-volatile) |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: industrial or commercial grade -21 suffix] |
| Encapsulado | 208-pin RQFP (Plastic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Tipo de montaje | Surface Mount | — |
| Lead-Free | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] | — |
| Estado RoHS | [DATA_NEEDED: not stated in retrieved distributor listings] | [DATA_NEEDED: confirm RoHS compliance for -21 variant] |
| Programmability | JTAG (IEEE 1149.1) in-system programming | — |
| Architecture | — | Multiple Array MatriX (MAX), third-generation |
| Technology | — | CMOS EEPROM-based |
| Flip-Flops | — | 772 |
| Maximum User I/O | — | 149 |
| Propagation Delay (speed grade -21) | — | 21 ns (max, per speed grade designation) |
| Tensión de alimentación | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (per variant) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| Security Bit | — | Yes (programmable) |