EPM9560RC208-19 vs EPM9560RC208-15 Comparación
Comparación detallada lado a lado de EPM9560RC208-19 por Altera y EPM9560RC208-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC208-19 | EPM9560RC208-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,20 | $0,00 |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Flip-Flops | 772 | — |
| User I/O Pins | 149 | — |
| Propagation Delay (tPD) | 19 ns | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V / 5 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| Technology | CMOS EEPROM | — |
| Encapsulado | RQFP-208 (208-pin PQFP) | 208-pin RQFP (Power Quad Flat Pack) |
| JEDEC Package Code | S-PQFP-G208 | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 9000 |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Tensión de alimentación | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |