EPM9560RC240-10 vs EPM9560RC240-1O Comparación
Comparación detallada lado a lado de EPM9560RC240-10 por Altera y EPM9560RC240-1O por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O ⚠ Última compraComparación de especificaciones
| Parámetro | EPM9560RC240-10 | EPM9560RC240-1O |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $51,07 |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 gates | 12,000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 12 | 35 |
| Maximum System Frequency | 144.9 MHz | — |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Tensión de alimentación | 5 V | — |
| Technology | CMOS EEPROM | — |
| Encapsulado | 240-pin RQFP (PowerQuad) | RQFP-240 (240-pin Reduced-height QFP) |
| User I/O Pins | 192 | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Estado RoHS | ROHS3 Compliant | Compliant (per Altera/Intel product page) |
| Configuration Memory | Non-volatile EEPROM (instant-on) | — |
| Manufacturer Standard Lead Time | 1-7 Days (distributor stock) | — |
| Macrocells | — | 560 |
| Maximum User I/O Pins | — | 216 |
| Propagation Delay (tPD) | — | 12 ns (typ, -1 speed grade) |
| Global Setup Time (tFSU) | — | 3.0 ns |
| Clock-to-Output (tFCO) | — | 4.8 ns |
| Maximum Internal Frequency (fCNT) | — | 145 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Grade) | — | -40C to +85C (industrial, "-1O" suffix) |
| Process Technology | — | CMOS EEPROM, 0.65 um |
| Programming | — | In-system programmable via IEEE 1149.1 JTAG |
| Architecture | — | Multiple Array MatriX (MAX), third generation |
| Lead-Free | — | Yes |