EPM9560RC240-10 vs EPM9560RC240-1O 对比

详细并排对比 EPM9560RC240-10 出自 Altera 和 EPM9560RC240-1O 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-10 EPM9560RC240-1O
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $0.00 $51.07
Device Type Complex Programmable Logic Device (CPLD) —
Family MAX 9000 MAX 9000
Usable Gates 12,000 gates 12,000
Macro Cells 560 —
Logic Array Blocks (LABs) 12 35
Maximum System Frequency 144.9 MHz —
Pin-to-Pin Propagation Delay 10 ns —
电源电压 5 V —
Technology CMOS EEPROM —
封装 240-pin RQFP (PowerQuad) RQFP-240 (240-pin Reduced-height QFP)
User I/O Pins 192 —
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (commercial) —
湿敏等级(MSL) 3 (168 Hours) —
RoHS 状态 ROHS3 Compliant Compliant (per Altera/Intel product page)
Configuration Memory Non-volatile EEPROM (instant-on) —
Manufacturer Standard Lead Time 1-7 Days (distributor stock) —
Macrocells — 560
Maximum User I/O Pins — 216
Propagation Delay (tPD) — 12 ns (typ, -1 speed grade)
Global Setup Time (tFSU) — 3.0 ns
Clock-to-Output (tFCO) — 4.8 ns
Maximum Internal Frequency (fCNT) — 145 MHz
Supply Voltage (VCC) — 5.0 V
Operating Temperature (Grade) — -40C to +85C (industrial, "-1O" suffix)
Process Technology — CMOS EEPROM, 0.65 um
Programming — In-system programmable via IEEE 1149.1 JTAG
Architecture — Multiple Array MatriX (MAX), third generation
Lead-Free — Yes

数据手册与资源

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