EPM9560RC240-15C vs EPM9560RC240-20N Comparación
Comparación detallada lado a lado de EPM9560RC240-15C por Intel y EPM9560RC240-20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC240-15C | EPM9560RC240-20N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based CPLD | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks | 20 | — |
| User I/O Pins | 187 | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Operating Voltage Range | 3.3 V or 5 V | — |
| Encapsulado | 240-pin RQFP (PowerQuad II) | 240-pin RQFP (PowerQuad Flat Pack) |
| Terminal Pitch | 0.5 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (in-system programmable) |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| Process Technology | CMOS | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Device Family | — | MAX 9000 (EPM9560) |
| Logic Type | — | Complex Programmable Logic Device (CPLD) |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Propagation Delay (tPD1) | — | 20 ns |
| Internal Counter Frequency (fCNT) | — | 144 MHz |
| Flip-Flop Setup Time (tSU) | — | 3.0 ns |
| Speed Grade | — | -20 (20 ns) |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |