EPM9560RC240-15N vs EPM9560RC240-20N Comparación
Comparación detallada lado a lado de EPM9560RC240-15N por Altera y EPM9560RC240-20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC240-15N | EPM9560RC240-20N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,85 | $0,00 |
| Series | MAX 9000 | — |
| Family | MAX 9000 (third-generation Multiple Array MatriX) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| Maximum User I/O Pins | 216 | 216 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Internal Counter Frequency (fCNT) | 145 MHz | 144 MHz |
| Global Setup Time (tFSU) | [DATA_NEEDED: tFSU for -15 grade] | — |
| Clock-to-Output Time (tFCO) | [DATA_NEEDED: tFCO for -15 grade] | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Logic Family | CMOS (EEPROM-based) | — |
| Programmability | In-system programmable (IEEE 1532/JTAG) | — |
| Boundary-Scan Test | JTAG (IEEE 1149.1) | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Encapsulado | RQFP-240 (240-pin Plastic Quad Flat Pack) | 240-pin RQFP (PowerQuad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 (EPM9560) |
| Logic Type | — | Complex Programmable Logic Device (CPLD) |
| Pin-to-Pin Propagation Delay (tPD1) | — | 20 ns |
| Flip-Flop Setup Time (tSU) | — | 3.0 ns |
| Configuration Technology | — | EEPROM (in-system programmable) |
| Speed Grade | — | -20 (20 ns) |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |